1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an active, or more broadly a metal-insulator semiconductor (MIS), pull-up circuit of a metal-oxide semiconductor (MOS) dynamic random access memory (RAM) device.
2. Description of the Prior Art
In dynamic RAM devices in which one-transistor one-capacitor type memory cells are primarily used, one sense amplifier for read operations is provided for each bit line pair. When a memory cell is selected, it generates only a small difference in potential between a pair of bit lines. The sense amplifier enlarges, i.e., amplifies the above-mentioned small difference in potential by pulling down the potential of the lower of the bit lines. However, when this occurs, the higher potential falls a little due to discharge at the sense amplifier immediately after the start of the sense operation, leakage currents after the completion of the operation, and the like. This is a disadvantage because the potential level for rewriting data into a memory cell is low. Therefore, an active pull-up circuit is used to pull up the higher potential of the bit lines.
An active pull-up circuit for each bit line basically comprises three elements, i.e., a first transistor connected between the bit line and a power supply, a second transistor connected between the gate of the first transistor and the bit line, and a capacitor connected to the gate of the first transistor. In order to drive this active pull-up circuit, a clock signal for controlling the gate potential of the second transistor, and a clock signal for controlling the capacitor potential are necessary. However, in recent years, an active pull-up circuit has been proposed in which the gate of the second transistor is connected to the bit line which shares the sense amplifier, so that the gate potential of the second transistor is controlled by the potential of this bit line. (See Japanese Unexamined Patent Publication (Kokai) No.53-120238). Such an active pull-up circuit connected to both bit lines in a pair has an advantage in that the control is simpler, since the number of clock signals is reduced.
In the above-mentioned active pull-up circuit connected to two bit lines, as will be explained in detail later, when a write operation for "reverse" data, opposite to that just sensed, is carried out on the same bit line pair after an active pull-up operation, it is impossible to carry out an active pull-up operation for the write operation. Therefore, the higher potential is not pulled up, which effects the following refresh operation. In addition, if the higher potential is reduced, the stored information can be erased.